A display panel drive circuit includes a shift register (10a) constructed of unit circuits (SC1 to SCm) connected in stages. The unit circuits generate signal line selection signals (G1 to Gm), respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. Each of the unit circuits receive (i) clock signals (CK1 and CK2) generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal (GSP) generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal (CLR). The clear signal (CLR) is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register (10a) until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal (VSYNC, HSYNC, or DE).